The present invention relates generally to an apparatus for screening high speed chips during mass production, and more particularly, to high speed chip screening via an algorithm in an embedded delay lock loop (DLL) that is read from a register through an interface by automated testing equipment (ATE).
High speed chips, such as a serializer/deserializer (serdes), advanced memory buffer (AMB), or the like can achieve speeds reaching several Giga-samples per second (GSa/s). During mass production, it is difficult to monitor the process variation and test the chip speed for compliance. Conventionally, the chip would include a built-in self-test (BIST) loop. By sweeping a reference clock through the BIST loop, the maximum speed of the chip could be determined. However, this procedure suffers from several drawbacks, particularly in the context of speed screening during mass production. For example, screening using the BIST is time-consuming due to the frequency sweeping. Further, the BIST is always a partial test and cannot cover the entire chip, and repeatability is a concern with BIST loops.
Another conventional screening technique includes the provision of a ring oscillator on the chip. The speed of the chip could be determined by measuring the frequency of the ring oscillator at an output, but an oscilloscope is required to perform the frequency measurement. Using an oscilloscope during production testing is very difficult, and often impossible. As a further complication to speed screening, ATE cannot test a high speed signal directly from the chip due to hardware limitations.
It is therefore desirable to provide an apparatus that enables accurate speed screening of high speed chips, reduces test times during mass production, is reliable and repeatable, and does not require the use of unnecessary testing instruments.